CS225,  Fall 2006, Monday, Dec.4, Day 41 after class

Take home exam available no later than Friday morning, due by noon Thursday Dec. 14
  --to me or to a Shilepsky personally, or all the way under my door.
HW Day 41, Due Wednesday Day 42  
Reading:
Warford,   Storage Management: 9.1,  thru p. 456.  9.2 thru 463.  Erratum p. 456 last paragraph: 3000 bytes 32 Kbytes.
HW to hand in:
p. 482,  #3 (for a and b:  they want unused bytes per file.  Your answer to b  will be only qualitative.  Part c should say:  "How would your answers to parts a and b change if you express the fragmentation by taking unused space as a percent of the file's allocated space, instead of the number of unused bytes."  Qualitative answers.)
#4.  You Need these facts:  Memory is byte-addressible.  Main (physical) memory is as large as addressible memory; that is, = in size to virtual memory.  For d assume the job can fill all of virtual memory.   
After answering a,b,c,d do this:  Assume that Main memory has only 6 of the possible 16 frames.  (So the frames are the same size as in part b.)  What (if any) answers to a,b,c,d will be different (and how)?  What is the smallest and what is the largest Physical address in Main memory?
#6  (hint:  which have been changed since being read in?)
#10 (Assume 3 frames are available.  Figure out what page to remove to put off the next  page fault  as long as possible. E.g. if  page 8 is going to be wanted in only 2 more steps, don't remove page 8 now.  (I suppose you could try to think ahead more than one page fault, but you're not asked to here.))  Present your result in a series of boxes like that of fig. 9.13, 9.16.

A) Continue with programming. 
Presentation to the world, Friday, Dec. 8, (in Study Week.) Time 1 to 2,    We will NOT be reworking any more code in class.
Post on the Wiki ASAP,  what you have working (however simple); or if not, something whose bugs you can't solve.
Have ready to hand in, Last class or at Presentation, printed out:
your code, cover pages (Sub documentation. Algorithm if not obvious), Self-evaluation (modified 11/27)

Amnesty extended again:  Any  old "Programs" handed in  by last day of classes will be only 1 day late.
 
= = = = = = = = = = == = = = =
Notes:
Chapter 9: Storage management, continued
9.1: Main memory  Increasingly complex techniques, each solving another problem.  continued
Multiprocessing techniques--  Each program should feel to itself as if it is running continuously in time and space.
  Relocatable techniques: 
   ...
 logical address Generate the object code as if it will be loaded at 0000.  This gives "logical addresses" for everything. 
                    Physical address = logical address + partition address       
           (Logical address is like index, offset from Base address of partition)

4) Paging:  ("paged memory")  Instead of adjusting the partitions to different sizes to fit the programs, break the memory into even size chunks (frames),  and break the program into pages (each the size of a frame).  Program pages get stuck into next available frames, not necessarily contiguous. 
Needs:  For each process:  1) keep track of where each page is (Page table).   
      Process 1:   Page     is in   Frame
                             1                   3
                             2                   8
                             3                   4
     2) Translate logical to physical addresses.  Need to know what page the instruction is on. 
                        Logical address = Page base address + offset
                            Page number<-->Frame number.
                      Physical = Frame base address + offset
         Efficient way to do this in the computer: 
            Make  page/frame size  a power of 2 (say 1 Kb) .
                 then logical address "splits'" at that place into page number + within-page address (offset).
            1Kb: 1024 = 210 addresses:  00 0000 0000 to 11 1111 1111  are the within-page addresses. (Least sig. 10 bits).
                    If we allow 26  pages, possible page/frame numbers are 0000 00 to 1111 11.  (Most sig. 6 bits).
            Logical Address 5D on page 3 is then 0000 11+00 0000 0101, or 0C05H    (216 total possible addresses: 16 bits long)
                   Since page 3 is in Frame 4,  
                       to get the Physical address we substitute the frame number for the page number, 0000 11-->0001 00
                            Physical address is 0001 00+00 0000 0101, or 1005H
           
  For op sys :   For each frame,  Keep track of which process and page is there--or empty.
      While program is running, every memory reference has to go through the page table. (at least if you're changing pages)

Problem:  Still some "internal fragmentation" --unusable space--because programs don't fill out the last page they use.  Unavoidable tradeoff:  Smaller page size cuts unusable space but increases overhead of managing larger page tables.  Faster circuitry for page table means more expense for larger table.

Problem:  Large processes may not fit into memory. 
   Solution:
9.2  Virtual Memory  (builds on paging)
Large process (job, program):  some parts used rarely, others heavily.  (Some data may never be used)
Working set: active pages of program.  Will change as program progresses.
Virtual memory:  Have (usually) more addresses (via page numbers) than you have memory (frame numbers.) e.g. Pep7 had 16-bit addresses  (could address 64K bytes) but only 32K of memory.   (in fact, the hard drive will have many many more addresses than you have memory)
Load pages from disk only as called for.  Remove an inactive page and replace it by a newly needed one.

Fig. 9.12, p. 457: all the things to track
  Each Process: Page table:  Page--Frame--Loaded?Y/N
   Memory view of itself:  Frame table:  Frame:  Process#/empty --Dirty?Y/N
"Dirty" : Remove a page: does it have to be rewritten to disk or is it unchanged? 
             No Stores happened to it--"clean", don't rewrite (e.g. reading straight code). 
              A Store changed contents--"dirty", must be rewritten to disk (e.g. changing variables/data).
Figure 9.12
Demand Paging: When the running program refers to an address, and the logical-->physical address translator discovers that page is not in memory, we have a Page Fault.   Causes interrupt, and OpSys figures out how to load in needed page.
If there is an Empty frame, fine.  Loads page, update Page and Frame tables, returns from interrupt & reloads PC with instruction that caused interrupt. (Now it will translate correctly)

No empty frame?  What page to replace??  FIFO, LRU (least recently used).  (Others.)  Algorithm depends on what is built in to hardware.   
Can keep track of FIFO with Queue of job-pages.  (p. 460 figure 9.13, 14.  Head of Queue is at bottom of picture, gets taken out.)
LRU with Queue-like linked list. When a page is used, move it to the tail of the Queue (top). (p. 460 fig. 9.15) Then the head (Bottom)  will have the least recently used page, gets taken out.
  Text:  Sequence of needed pages: 6 8 3 8 6 0 3 6 3 5 3 6.  The F's refer to the Fault just before the resulting swapping in the picture just above.

That was concept:  In practice:

Virtual Memory   (definitions via Google . from http://www.upgradememory.com/Computer_Memory_Glossary_W10C15775.cfm?NBP=1)
When all physical memory (i.e., installed memory modules) are being used, the system can simulate more memory by using empty sectors in the hard drive to store additional data. The process of storing extra data on the hard drive and treating it as extra memory is known as swapping. Since hard drive access times are much slower than memory access times (about 60,000 times slower), using virtual memory can severely decrease performance if it is commonly performed.

Intermediate solution:--grades of memory
Cache Memory
High-speed static RAM (SRAM) directly connected to the CPU, usually between 256KB-2MB. Cache memory operates like a "frequently used data" file for your CPU. The cache dynamically stores and accesses the data your CPU and applications access most often so that it can be more quickly retrieved. The larger the cache, the better the performance of your system, since more data can be retrieved with high speed. There are two types of cache memory:

That's all the Internals stuff we'll do, I think.  I encourage you to read (for pleasure and edification) as much more of Ch.8 and 9 as you can stand, but it's not required for the course.

Wednesday??  Hmm.  Stay tuned.

, To Sievers Home Page
CS225-Fall06/Day40.htm 
1pm, 12/3/06
This page belongs to Sally Sievers who is solely responsible for its content. Please see our statement of responsibility